High electrical performance and cost effective package technologies require a holistic design co-simulation approach that comprehends the interconnect continuum including silicon die, wirebond, substrate and PCB board. Due to current trends in IC design that increased device functionality and complexity, so as the demand of high signal transmission quality and power efficient electronic device, electrical integrity analysis becomes a crucial requirements.
ASEM electrical simulation team is dedicated to provide IC package electrical characteristics and analysis in terms of signal integrity & power integrity to meet the package high electrical performance specifications. ASEM also work closely with designers and customers to co-design custom IC packaging especially for high speed solutions.
Customer can utilize the information to optimize the design by making modification prior to fabrication which can reduce cycle time to market and cost.
- Impedance Control Analysis
- Parasitic Extraction (RLC & Delay) for Traces
- Parasitic Extraction for Power / Ground
- S-parameter Extraction
- IBIS / SPICE / Touchstone Model
- Signal Integrity Analysis (Return/Insertion Loss, Cross Talk)
- Power Integrity Analysis (Voltage Drop, current density, power loss)
- High speed & high electrical performance solutions
- Ansoft Q2D Extractor
- Ansoft Q3D Extractor
- Ansoft HFSS
- Sigrity XtractIM
- Sigrity Power SI
- Sigrity Power DC
- Agilent Advanced Design System (ADS)